\doxysection{C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/cmsis\+\_\+armclang\+\_\+ltm.h File Reference}
\hypertarget{cmsis__armclang__ltm_8h}{}\label{cmsis__armclang__ltm_8h}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/cmsis\_armclang\_ltm.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/cmsis\_armclang\_ltm.h}}


CMSIS compiler armclang (Arm Compiler 6) header file.  


{\ttfamily \#include $<$arm\+\_\+compat.\+h$>$}\newline
\doxysubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a1378040bcf22428955c6e3ce9c2053cd}\label{cmsis__armclang__ltm_8h_a1378040bcf22428955c6e3ce9c2053cd} 
\#define {\bfseries \+\_\+\+\_\+\+ASM}~\+\_\+\+\_\+asm
\item 
\Hypertarget{cmsis__armclang__ltm_8h_ade2d8d7118f8ff49547f60aa0c3382bb}\label{cmsis__armclang__ltm_8h_ade2d8d7118f8ff49547f60aa0c3382bb} 
\#define {\bfseries \+\_\+\+\_\+\+INLINE}~\+\_\+\+\_\+inline
\item 
\Hypertarget{cmsis__armclang__ltm_8h_aba87361bfad2ae52cfe2f40c1a1dbf9c}\label{cmsis__armclang__ltm_8h_aba87361bfad2ae52cfe2f40c1a1dbf9c} 
\#define {\bfseries \+\_\+\+\_\+\+STATIC\+\_\+\+INLINE}~static \+\_\+\+\_\+inline
\item 
\Hypertarget{cmsis__armclang__ltm_8h_ab904513442afdf77d4f8c74f23cbb040}\label{cmsis__armclang__ltm_8h_ab904513442afdf77d4f8c74f23cbb040} 
\#define {\bfseries \+\_\+\+\_\+\+STATIC\+\_\+\+FORCEINLINE}~\+\_\+\+\_\+attribute\+\_\+\+\_\+((always\+\_\+inline)) static \+\_\+\+\_\+inline
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a153a4a31b276a9758959580538720a51}\label{cmsis__armclang__ltm_8h_a153a4a31b276a9758959580538720a51} 
\#define {\bfseries \+\_\+\+\_\+\+NO\+\_\+\+RETURN}~\+\_\+\+\_\+attribute\+\_\+\+\_\+((\+\_\+\+\_\+noreturn\+\_\+\+\_\+))
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a3e40e4c553fc11588f7a4c2a19e789e0}\label{cmsis__armclang__ltm_8h_a3e40e4c553fc11588f7a4c2a19e789e0} 
\#define {\bfseries \+\_\+\+\_\+\+USED}~\+\_\+\+\_\+attribute\+\_\+\+\_\+((used))
\item 
\Hypertarget{cmsis__armclang__ltm_8h_ac607bf387b29162be6a9b77fc7999539}\label{cmsis__armclang__ltm_8h_ac607bf387b29162be6a9b77fc7999539} 
\#define {\bfseries \+\_\+\+\_\+\+WEAK}~\+\_\+\+\_\+attribute\+\_\+\+\_\+((weak))
\item 
\Hypertarget{cmsis__armclang__ltm_8h_abe8996d3d985ee1529475443cc635bf1}\label{cmsis__armclang__ltm_8h_abe8996d3d985ee1529475443cc635bf1} 
\#define {\bfseries \+\_\+\+\_\+\+PACKED}~\+\_\+\+\_\+attribute\+\_\+\+\_\+((packed, aligned(1)))
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a4dbb70fab85207c27b581ecb6532b314}\label{cmsis__armclang__ltm_8h_a4dbb70fab85207c27b581ecb6532b314} 
\#define {\bfseries \+\_\+\+\_\+\+PACKED\+\_\+\+STRUCT}~struct \+\_\+\+\_\+attribute\+\_\+\+\_\+((packed, aligned(1)))
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a6fba34d08b0a526830b4231d2ea0b89a}\label{cmsis__armclang__ltm_8h_a6fba34d08b0a526830b4231d2ea0b89a} 
\#define {\bfseries \+\_\+\+\_\+\+PACKED\+\_\+\+UNION}~union \+\_\+\+\_\+attribute\+\_\+\+\_\+((packed, aligned(1)))
\item 
\#define \mbox{\hyperlink{cmsis__armclang__ltm_8h_ac8a13aacd0453758fdfd01a57a2a6a3d}{\+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT32}}(x)
\item 
\#define \mbox{\hyperlink{cmsis__armclang__ltm_8h_a5103fb373cae9837cc4a384be55dc87f}{\+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT16\+\_\+\+WRITE}}(addr,  val)
\item 
\#define \mbox{\hyperlink{cmsis__armclang__ltm_8h_ab71b66e5ce403158d3dee62a59f9175f}{\+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT16\+\_\+\+READ}}(addr)
\item 
\#define \mbox{\hyperlink{cmsis__armclang__ltm_8h_a203f593d140ed88b81bc189edc861110}{\+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT32\+\_\+\+WRITE}}(addr,  val)
\item 
\#define \mbox{\hyperlink{cmsis__armclang__ltm_8h_a3b931f0b051b8c1a6377a3dcc7559b5e}{\+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT32\+\_\+\+READ}}(addr)
\item 
\#define \mbox{\hyperlink{cmsis__armclang__ltm_8h_aa65ef8f7a5e8b7a6ea6c1d48b4c78e55}{\+\_\+\+\_\+\+ALIGNED}}(x)
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a378ac21329d33f561f90265eef89f564}\label{cmsis__armclang__ltm_8h_a378ac21329d33f561f90265eef89f564} 
\#define {\bfseries \+\_\+\+\_\+\+RESTRICT}~\+\_\+\+\_\+restrict
\item 
\#define \mbox{\hyperlink{cmsis__armclang__ltm_8h_a6516fb12ab0dd45c734f8cef7d921af6}{\+\_\+\+\_\+\+COMPILER\+\_\+\+BARRIER}}()
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a72db8b026c5e100254080fefabd9fd88}\label{cmsis__armclang__ltm_8h_a72db8b026c5e100254080fefabd9fd88} 
\#define {\bfseries \+\_\+\+\_\+\+PROGRAM\+\_\+\+START}~\+\_\+\+\_\+main
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a1002e751427b1189f92787d4e4eef965}\label{cmsis__armclang__ltm_8h_a1002e751427b1189f92787d4e4eef965} 
\#define {\bfseries \+\_\+\+\_\+\+INITIAL\+\_\+\+SP}~Image\$\$\+ARM\+\_\+\+LIB\+\_\+\+STACK\$\$\+ZI\$\$\+Limit
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a84b0bad4aa39632d3faea46aa1e102a8}\label{cmsis__armclang__ltm_8h_a84b0bad4aa39632d3faea46aa1e102a8} 
\#define {\bfseries \+\_\+\+\_\+\+STACK\+\_\+\+LIMIT}~Image\$\$\+ARM\+\_\+\+LIB\+\_\+\+STACK\$\$\+ZI\$\$\+Base
\item 
\Hypertarget{cmsis__armclang__ltm_8h_ab94ebeb20055f1848d7b707d3c7cfc5d}\label{cmsis__armclang__ltm_8h_ab94ebeb20055f1848d7b707d3c7cfc5d} 
\#define {\bfseries \+\_\+\+\_\+\+VECTOR\+\_\+\+TABLE}~\+\_\+\+\_\+\+Vectors
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a4f65c96effa79fbd610fea43ee7d745b}\label{cmsis__armclang__ltm_8h_a4f65c96effa79fbd610fea43ee7d745b} 
\#define {\bfseries \+\_\+\+\_\+\+VECTOR\+\_\+\+TABLE\+\_\+\+ATTRIBUTE}~\+\_\+\+\_\+attribute((used, section("{}RESET"{})))
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga6b3a48e13de4b114653b4e06145a601d}{\+\_\+\+\_\+get\+\_\+\+FPSCR}}()
\begin{DoxyCompactList}\small\item\em Get FPSCR. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga3cd91c42ad2793c3f3ae553a1b975512}{\+\_\+\+\_\+set\+\_\+\+FPSCR}}(x)
\begin{DoxyCompactList}\small\item\em Set FPSCR. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabc17e391c13c71702366c67cba39c276}{\+\_\+\+\_\+\+CMSIS\+\_\+\+GCC\+\_\+\+OUT\+\_\+\+REG}}(r)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga9d94dee7402367961d2cf0accc00fd97}{\+\_\+\+\_\+\+CMSIS\+\_\+\+GCC\+\_\+\+USE\+\_\+\+REG}}(r)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabd585ddc865fb9b7f2493af1eee1a572}{\+\_\+\+\_\+\+NOP}}~\+\_\+\+\_\+builtin\+\_\+arm\+\_\+nop
\begin{DoxyCompactList}\small\item\em No Operation. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gad23bf2b78a9a4524157c9de0d30b7448}{\+\_\+\+\_\+\+WFI}}~\+\_\+\+\_\+builtin\+\_\+arm\+\_\+wfi
\begin{DoxyCompactList}\small\item\em Wait For Interrupt. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaac6cc7dd4325d9cb40d3290fa5244b3d}{\+\_\+\+\_\+\+WFE}}~\+\_\+\+\_\+builtin\+\_\+arm\+\_\+wfe
\begin{DoxyCompactList}\small\item\em Wait For Event. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaab4f296d0022b4b10dc0976eb22052f9}{\+\_\+\+\_\+\+SEV}}~\+\_\+\+\_\+builtin\+\_\+arm\+\_\+sev
\begin{DoxyCompactList}\small\item\em Send Event. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\+\_\+\+\_\+\+ISB}}()
\begin{DoxyCompactList}\small\item\em Instruction Synchronization Barrier. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\+\_\+\+\_\+\+DSB}}()
\begin{DoxyCompactList}\small\item\em Data Synchronization Barrier. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga671101179b5943990785f36f8c1e2269}{\+\_\+\+\_\+\+DMB}}()
\begin{DoxyCompactList}\small\item\em Data Memory Barrier. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaca25a02e09983da5558f5242f2f635bc}{\+\_\+\+\_\+\+REV}}(value)
\begin{DoxyCompactList}\small\item\em Reverse byte order (32 bit) \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gad35497777af37e7809271b5e6f9510ba}{\+\_\+\+\_\+\+REV16}}(value)
\begin{DoxyCompactList}\small\item\em Reverse byte order (16 bit) \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gae580812686119c9c5cf3c11a7519a404}{\+\_\+\+\_\+\+REVSH}}(value)
\begin{DoxyCompactList}\small\item\em Reverse byte order (16 bit) \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga15ea6bd3c507d3e81c3b3a1258e46397}{\+\_\+\+\_\+\+BKPT}}(value)
\begin{DoxyCompactList}\small\item\em Breakpoint. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gab83768933a612816fad669db5488366f}{\+\_\+\+\_\+\+RBIT}}~\+\_\+\+\_\+builtin\+\_\+arm\+\_\+rbit
\begin{DoxyCompactList}\small\item\em Reverse bit order of value. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
\Hypertarget{cmsis__armclang__ltm_8h_ade51b179ed6f69a6bacfab38b7b359b1}\label{cmsis__armclang__ltm_8h_ade51b179ed6f69a6bacfab38b7b359b1} 
struct {\bfseries \+\_\+\+\_\+attribute\+\_\+\+\_\+} ((packed)) T\+\_\+\+UINT32
\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga7dd5c942bee32f055b90153feb950f59}{\+\_\+\+\_\+get\+\_\+\+CONTROL}} (void)
\begin{DoxyCompactList}\small\item\em Enable IRQ Interrupts. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE void \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga0102d0939d9b26c5c792be6bf5fd550f}{\+\_\+\+\_\+set\+\_\+\+CONTROL}} (uint32\+\_\+t control)
\begin{DoxyCompactList}\small\item\em Set Control Register. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_gaf15a71855b9d731d11de92704c82bd18}{\+\_\+\+\_\+get\+\_\+\+IPSR}} (void)
\begin{DoxyCompactList}\small\item\em Get IPSR Register. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_gadff4f1e599946e8ae96fba17b5245f04}{\+\_\+\+\_\+get\+\_\+\+APSR}} (void)
\begin{DoxyCompactList}\small\item\em Get APSR Register. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga94c675a736d4754a5f73d8748b24aa11}{\+\_\+\+\_\+get\+\_\+x\+PSR}} (void)
\begin{DoxyCompactList}\small\item\em Get x\+PSR Register. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga826c53e30812e350c77f58aac9f42bcb}{\+\_\+\+\_\+get\+\_\+\+PSP}} (void)
\begin{DoxyCompactList}\small\item\em Get Process Stack Pointer. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE void \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga21f50fc02c3927a8ebf0bc3678c06862}{\+\_\+\+\_\+set\+\_\+\+PSP}} (uint32\+\_\+t top\+Of\+Proc\+Stack)
\begin{DoxyCompactList}\small\item\em Set Process Stack Pointer. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga667e7b8b97b4a30f445ae45d37588e45}{\+\_\+\+\_\+get\+\_\+\+MSP}} (void)
\begin{DoxyCompactList}\small\item\em Get Main Stack Pointer. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE void \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga08b66e2b60a46fada36d90d2bc1e7c9b}{\+\_\+\+\_\+set\+\_\+\+MSP}} (uint32\+\_\+t top\+Of\+Main\+Stack)
\begin{DoxyCompactList}\small\item\em Set Main Stack Pointer. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_ga4ff59fb9e280d19e79e6875863a65f0a}{\+\_\+\+\_\+get\+\_\+\+PRIMASK}} (void)
\begin{DoxyCompactList}\small\item\em Get Priority Mask. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+INLINE void \mbox{\hyperlink{group___c_m_s_i_s___core___reg_acc_functions_gaf4a17d3be7dbb066489836d849930d92}{\+\_\+\+\_\+set\+\_\+\+PRIMASK}} (uint32\+\_\+t pri\+Mask)
\begin{DoxyCompactList}\small\item\em Set Priority Mask. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+FORCEINLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gab16acb6456176f1e87a4f2724c2b6028}{\+\_\+\+\_\+\+ROR}} (uint32\+\_\+t op1, uint32\+\_\+t op2)
\begin{DoxyCompactList}\small\item\em Rotate Right in unsigned value (32 bit) \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+FORCEINLINE uint8\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaf32ee2525f946bce31504904f3ef8243}{\+\_\+\+\_\+\+CLZ}} (uint32\+\_\+t value)
\begin{DoxyCompactList}\small\item\em Count leading zeros. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+FORCEINLINE int32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga372c0535573dde3e37f0f08c774a3487}{\+\_\+\+\_\+\+SSAT}} (int32\+\_\+t val, uint32\+\_\+t sat)
\begin{DoxyCompactList}\small\item\em Signed Saturate. \end{DoxyCompactList}\item 
\+\_\+\+\_\+\+STATIC\+\_\+\+FORCEINLINE uint32\+\_\+t \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga6562dbd8182d1571e22dbca7ebdfa9bc}{\+\_\+\+\_\+\+USAT}} (int32\+\_\+t val, uint32\+\_\+t sat)
\begin{DoxyCompactList}\small\item\em Unsigned Saturate. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Variables}
\begin{DoxyCompactItemize}
\item 
\Hypertarget{cmsis__armclang__ltm_8h_ac962a9aa89cef6e5cde0fe6b067f7de3}\label{cmsis__armclang__ltm_8h_ac962a9aa89cef6e5cde0fe6b067f7de3} 
\+\_\+\+\_\+\+PACKED\+\_\+\+STRUCT {\bfseries T\+\_\+\+UINT16\+\_\+\+WRITE} \{ uint16\+\_\+t v
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a86899dc41c5b3b9ce6b8014ee0e852b9}\label{cmsis__armclang__ltm_8h_a86899dc41c5b3b9ce6b8014ee0e852b9} 
\+\_\+\+\_\+\+PACKED\+\_\+\+STRUCT {\bfseries T\+\_\+\+UINT16\+\_\+\+READ} \{ uint16\+\_\+t v
\item 
\Hypertarget{cmsis__armclang__ltm_8h_abbd193dec7cb45f1fbd05ff7e366ffe2}\label{cmsis__armclang__ltm_8h_abbd193dec7cb45f1fbd05ff7e366ffe2} 
\+\_\+\+\_\+\+PACKED\+\_\+\+STRUCT {\bfseries T\+\_\+\+UINT32\+\_\+\+WRITE} \{ uint32\+\_\+t v
\item 
\Hypertarget{cmsis__armclang__ltm_8h_a9653a1cbf01ec418e8e940ee3996b8ca}\label{cmsis__armclang__ltm_8h_a9653a1cbf01ec418e8e940ee3996b8ca} 
\+\_\+\+\_\+\+PACKED\+\_\+\+STRUCT {\bfseries T\+\_\+\+UINT32\+\_\+\+READ} \{ uint32\+\_\+t v
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
CMSIS compiler armclang (Arm Compiler 6) header file. 

\begin{DoxyVersion}{Version}
V1.\+2.\+0 
\end{DoxyVersion}
\begin{DoxyDate}{Date}
08. May 2019 
\end{DoxyDate}


\label{doc-define-members}
\Hypertarget{cmsis__armclang__ltm_8h_doc-define-members}
\doxysubsection{Macro Definition Documentation}
\Hypertarget{cmsis__armclang__ltm_8h_aa65ef8f7a5e8b7a6ea6c1d48b4c78e55}\index{cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}!\_\_ALIGNED@{\_\_ALIGNED}}
\index{\_\_ALIGNED@{\_\_ALIGNED}!cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}}
\doxysubsubsection{\texorpdfstring{\_\_ALIGNED}{\_\_ALIGNED}}
{\footnotesize\ttfamily \label{cmsis__armclang__ltm_8h_aa65ef8f7a5e8b7a6ea6c1d48b4c78e55} 
\#define \+\_\+\+\_\+\+ALIGNED(\begin{DoxyParamCaption}\item[{}]{x}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\_\_attribute\_\_((aligned(x)))}

\end{DoxyCode}
\Hypertarget{cmsis__armclang__ltm_8h_a6516fb12ab0dd45c734f8cef7d921af6}\index{cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}!\_\_COMPILER\_BARRIER@{\_\_COMPILER\_BARRIER}}
\index{\_\_COMPILER\_BARRIER@{\_\_COMPILER\_BARRIER}!cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}}
\doxysubsubsection{\texorpdfstring{\_\_COMPILER\_BARRIER}{\_\_COMPILER\_BARRIER}}
{\footnotesize\ttfamily \label{cmsis__armclang__ltm_8h_a6516fb12ab0dd45c734f8cef7d921af6} 
\#define \+\_\+\+\_\+\+COMPILER\+\_\+\+BARRIER(\begin{DoxyParamCaption}{}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{\_\_ASM\ \textcolor{keyword}{volatile}(\textcolor{stringliteral}{"{}"{}}:::\textcolor{stringliteral}{"{}memory"{}})}

\end{DoxyCode}
\Hypertarget{cmsis__armclang__ltm_8h_ab71b66e5ce403158d3dee62a59f9175f}\index{cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}!\_\_UNALIGNED\_UINT16\_READ@{\_\_UNALIGNED\_UINT16\_READ}}
\index{\_\_UNALIGNED\_UINT16\_READ@{\_\_UNALIGNED\_UINT16\_READ}!cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}}
\doxysubsubsection{\texorpdfstring{\_\_UNALIGNED\_UINT16\_READ}{\_\_UNALIGNED\_UINT16\_READ}}
{\footnotesize\ttfamily \label{cmsis__armclang__ltm_8h_ab71b66e5ce403158d3dee62a59f9175f} 
\#define \+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT16\+\_\+\+READ(\begin{DoxyParamCaption}\item[{}]{addr}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{(((\textcolor{keyword}{const}\ \textcolor{keyword}{struct\ }T\_UINT16\_READ\ *)(\textcolor{keyword}{const}\ \textcolor{keywordtype}{void}\ *)(addr))-\/>v)}

\end{DoxyCode}
\Hypertarget{cmsis__armclang__ltm_8h_a5103fb373cae9837cc4a384be55dc87f}\index{cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}!\_\_UNALIGNED\_UINT16\_WRITE@{\_\_UNALIGNED\_UINT16\_WRITE}}
\index{\_\_UNALIGNED\_UINT16\_WRITE@{\_\_UNALIGNED\_UINT16\_WRITE}!cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}}
\doxysubsubsection{\texorpdfstring{\_\_UNALIGNED\_UINT16\_WRITE}{\_\_UNALIGNED\_UINT16\_WRITE}}
{\footnotesize\ttfamily \label{cmsis__armclang__ltm_8h_a5103fb373cae9837cc4a384be55dc87f} 
\#define \+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT16\+\_\+\+WRITE(\begin{DoxyParamCaption}\item[{}]{addr}{, }\item[{}]{val}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{(void)((((\textcolor{keyword}{struct}\ T\_UINT16\_WRITE\ *)(\textcolor{keywordtype}{void}\ *)(addr))-\/>v)\ =\ (val))}

\end{DoxyCode}
\Hypertarget{cmsis__armclang__ltm_8h_ac8a13aacd0453758fdfd01a57a2a6a3d}\index{cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}!\_\_UNALIGNED\_UINT32@{\_\_UNALIGNED\_UINT32}}
\index{\_\_UNALIGNED\_UINT32@{\_\_UNALIGNED\_UINT32}!cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}}
\doxysubsubsection{\texorpdfstring{\_\_UNALIGNED\_UINT32}{\_\_UNALIGNED\_UINT32}}
{\footnotesize\ttfamily \label{cmsis__armclang__ltm_8h_ac8a13aacd0453758fdfd01a57a2a6a3d} 
\#define \+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT32(\begin{DoxyParamCaption}\item[{}]{x}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{(((\textcolor{keyword}{struct\ }T\_UINT32\ *)(x))-\/>v)}

\end{DoxyCode}
\Hypertarget{cmsis__armclang__ltm_8h_a3b931f0b051b8c1a6377a3dcc7559b5e}\index{cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}!\_\_UNALIGNED\_UINT32\_READ@{\_\_UNALIGNED\_UINT32\_READ}}
\index{\_\_UNALIGNED\_UINT32\_READ@{\_\_UNALIGNED\_UINT32\_READ}!cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}}
\doxysubsubsection{\texorpdfstring{\_\_UNALIGNED\_UINT32\_READ}{\_\_UNALIGNED\_UINT32\_READ}}
{\footnotesize\ttfamily \label{cmsis__armclang__ltm_8h_a3b931f0b051b8c1a6377a3dcc7559b5e} 
\#define \+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT32\+\_\+\+READ(\begin{DoxyParamCaption}\item[{}]{addr}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{(((\textcolor{keyword}{const}\ \textcolor{keyword}{struct\ }T\_UINT32\_READ\ *)(\textcolor{keyword}{const}\ \textcolor{keywordtype}{void}\ *)(addr))-\/>v)}

\end{DoxyCode}
\Hypertarget{cmsis__armclang__ltm_8h_a203f593d140ed88b81bc189edc861110}\index{cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}!\_\_UNALIGNED\_UINT32\_WRITE@{\_\_UNALIGNED\_UINT32\_WRITE}}
\index{\_\_UNALIGNED\_UINT32\_WRITE@{\_\_UNALIGNED\_UINT32\_WRITE}!cmsis\_armclang\_ltm.h@{cmsis\_armclang\_ltm.h}}
\doxysubsubsection{\texorpdfstring{\_\_UNALIGNED\_UINT32\_WRITE}{\_\_UNALIGNED\_UINT32\_WRITE}}
{\footnotesize\ttfamily \label{cmsis__armclang__ltm_8h_a203f593d140ed88b81bc189edc861110} 
\#define \+\_\+\+\_\+\+UNALIGNED\+\_\+\+UINT32\+\_\+\+WRITE(\begin{DoxyParamCaption}\item[{}]{addr}{, }\item[{}]{val}{}\end{DoxyParamCaption})}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{(void)((((\textcolor{keyword}{struct}\ T\_UINT32\_WRITE\ *)(\textcolor{keywordtype}{void}\ *)(addr))-\/>v)\ =\ (val))}

\end{DoxyCode}
